mirror of
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CHECKP: shitty VFS
This commit is contained in:
boreddevnl
509
src/dev/ahci.c
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509
src/dev/ahci.c
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@@ -0,0 +1,509 @@
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// Copyright (c) 2023-2026 Chris (boreddevnl)
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// This software is released under the GNU General Public License v3.0. See LICENSE file for details.
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// This header needs to maintain in any file it is present in, as per the GPL license terms.
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#include "ahci.h"
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#include "pci.h"
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#include "disk.h"
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#include "memory_manager.h"
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#include "paging.h"
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#include "io.h"
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#include <stddef.h>
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extern void serial_write(const char *str);
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extern void serial_write_num(uint64_t num);
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extern void serial_write_hex(uint32_t val);
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// ============================================================================
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// AHCI Driver State
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// ============================================================================
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static HBA_MEM *abar = NULL; // MMIO-mapped AHCI Base Address
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static bool ahci_initialized = false;
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static int active_port_count = 0;
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#define MAX_AHCI_PORTS 32
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typedef struct {
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bool active;
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int port_num;
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HBA_PORT *port;
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HBA_CMD_HEADER *cmd_list; // 1KB, 1KB aligned
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void *fis_base; // 256B, 256B aligned
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HBA_CMD_TBL *cmd_tbl; // Command table for slot 0
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} ahci_port_state_t;
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static ahci_port_state_t ports[MAX_AHCI_PORTS];
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// ============================================================================
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// String Helpers
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// ============================================================================
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static void ahci_strcpy(char *d, const char *s) {
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while ((*d++ = *s++));
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}
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// Kernel virtual to physical address conversion
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extern uint64_t v2p(uint64_t vaddr);
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// ============================================================================
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// Port Setup
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// ============================================================================
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static void ahci_stop_cmd(HBA_PORT *port) {
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// Clear ST (Start)
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port->cmd &= ~HBA_PORT_CMD_ST;
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// Clear FRE (FIS Receive Enable)
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port->cmd &= ~HBA_PORT_CMD_FRE;
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// Wait until FR and CR clear
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int timeout = 500000;
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while (timeout-- > 0) {
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if (port->cmd & HBA_PORT_CMD_FR) continue;
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if (port->cmd & HBA_PORT_CMD_CR) continue;
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break;
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}
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}
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static void ahci_start_cmd(HBA_PORT *port) {
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// Wait until CR clears
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while (port->cmd & HBA_PORT_CMD_CR);
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// Set FRE and ST
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port->cmd |= HBA_PORT_CMD_FRE;
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port->cmd |= HBA_PORT_CMD_ST;
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}
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static int ahci_check_port_type(HBA_PORT *port) {
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uint32_t ssts = port->ssts;
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uint8_t ipm = (ssts >> 8) & 0x0F;
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uint8_t det = ssts & 0x0F;
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if (det != 3) return -1; // No device detected
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if (ipm != 1) return -1; // Not in active state
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switch (port->sig) {
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case SATA_SIG_ATA: return 0; // SATA drive
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case SATA_SIG_ATAPI: return 1; // SATAPI drive
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case SATA_SIG_SEMB: return 2; // SEMB
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case SATA_SIG_PM: return 3; // Port multiplier
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default: return -1;
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}
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}
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static void ahci_port_rebase(ahci_port_state_t *ps) {
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HBA_PORT *port = ps->port;
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ahci_stop_cmd(port);
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// Allocate command list (1KB, 1024-byte aligned)
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ps->cmd_list = (HBA_CMD_HEADER*)kmalloc_aligned(1024, 1024);
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if (!ps->cmd_list) return;
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mem_memset(ps->cmd_list, 0, 1024);
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uint64_t clb_phys = v2p((uint64_t)ps->cmd_list);
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port->clb = (uint32_t)(clb_phys & 0xFFFFFFFF);
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port->clbu = (uint32_t)(clb_phys >> 32);
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// Allocate FIS receive area (256 bytes, 256-byte aligned)
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ps->fis_base = kmalloc_aligned(256, 256);
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if (!ps->fis_base) return;
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mem_memset(ps->fis_base, 0, 256);
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uint64_t fb_phys = v2p((uint64_t)ps->fis_base);
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port->fb = (uint32_t)(fb_phys & 0xFFFFFFFF);
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port->fbu = (uint32_t)(fb_phys >> 32);
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// Allocate command table for slot 0 (256-byte aligned, room for 8 PRDT entries)
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int cmd_tbl_size = sizeof(HBA_CMD_TBL) + 8 * sizeof(HBA_PRDT_ENTRY);
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ps->cmd_tbl = (HBA_CMD_TBL*)kmalloc_aligned(cmd_tbl_size, 256);
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if (!ps->cmd_tbl) return;
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mem_memset(ps->cmd_tbl, 0, cmd_tbl_size);
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// Set command header 0 to point to our command table
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uint64_t ctba_phys = v2p((uint64_t)ps->cmd_tbl);
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ps->cmd_list[0].ctba = (uint32_t)(ctba_phys & 0xFFFFFFFF);
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ps->cmd_list[0].ctbau = (uint32_t)(ctba_phys >> 32);
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ps->cmd_list[0].prdtl = 1; // 1 PRDT entry default
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// Clear error and interrupt status
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port->serr = 0xFFFFFFFF;
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port->is = 0xFFFFFFFF;
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ahci_start_cmd(port);
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}
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// ============================================================================
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// Sector I/O
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// ============================================================================
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static int ahci_find_free_slot(HBA_PORT *port) {
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uint32_t slots = (port->sact | port->ci);
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for (int i = 0; i < 32; i++) {
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if (!(slots & (1 << i))) return i;
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}
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return -1;
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}
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int ahci_read_sectors(int port_num, uint64_t lba, uint32_t count, uint8_t *buffer) {
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if (!ahci_initialized || port_num < 0 || port_num >= MAX_AHCI_PORTS) return -1;
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ahci_port_state_t *ps = &ports[port_num];
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if (!ps->active) return -1;
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HBA_PORT *port = ps->port;
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// Clear any pending interrupts/errors
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port->is = 0xFFFFFFFF;
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int slot = ahci_find_free_slot(port);
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if (slot < 0) return -1;
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HBA_CMD_HEADER *cmd_hdr = &ps->cmd_list[slot];
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cmd_hdr->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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cmd_hdr->w = 0; // Read
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cmd_hdr->prdtl = 1;
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HBA_CMD_TBL *cmd_tbl = ps->cmd_tbl;
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mem_memset(cmd_tbl, 0, sizeof(HBA_CMD_TBL) + sizeof(HBA_PRDT_ENTRY));
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// Setup PRDT
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uint64_t buf_phys = v2p((uint64_t)buffer);
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cmd_tbl->prdt[0].dba = (uint32_t)(buf_phys & 0xFFFFFFFF);
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cmd_tbl->prdt[0].dbau = (uint32_t)(buf_phys >> 32);
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cmd_tbl->prdt[0].dbc = (count * 512) - 1; // 0-based byte count
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cmd_tbl->prdt[0].i = 1;
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// Setup Command FIS
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FIS_REG_H2D *fis = (FIS_REG_H2D*)&cmd_tbl->cfis;
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1; // Command
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fis->command = ATA_CMD_READ_DMA_EX;
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fis->lba0 = (uint8_t)(lba);
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fis->lba1 = (uint8_t)(lba >> 8);
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fis->lba2 = (uint8_t)(lba >> 16);
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fis->device = 1 << 6; // LBA mode
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fis->lba3 = (uint8_t)(lba >> 24);
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fis->lba4 = (uint8_t)(lba >> 32);
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fis->lba5 = (uint8_t)(lba >> 40);
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fis->countl = (uint8_t)(count);
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fis->counth = (uint8_t)(count >> 8);
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// Issue command
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port->ci = (1 << slot);
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// Wait for completion
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int timeout = 1000000;
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while (timeout-- > 0) {
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if (!(port->ci & (1 << slot))) break;
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if (port->is & (1 << 30)) { // Task File Error
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serial_write("[AHCI] Read error on port ");
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serial_write_num(port_num);
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serial_write("\n");
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return -1;
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}
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}
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if (timeout <= 0) {
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serial_write("[AHCI] Read timeout on port ");
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serial_write_num(port_num);
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serial_write("\n");
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return -1;
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}
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return 0;
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}
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int ahci_write_sectors(int port_num, uint64_t lba, uint32_t count, const uint8_t *buffer) {
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if (!ahci_initialized || port_num < 0 || port_num >= MAX_AHCI_PORTS) return -1;
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ahci_port_state_t *ps = &ports[port_num];
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if (!ps->active) return -1;
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HBA_PORT *port = ps->port;
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port->is = 0xFFFFFFFF;
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int slot = ahci_find_free_slot(port);
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if (slot < 0) return -1;
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HBA_CMD_HEADER *cmd_hdr = &ps->cmd_list[slot];
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cmd_hdr->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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cmd_hdr->w = 1; // Write
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cmd_hdr->prdtl = 1;
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HBA_CMD_TBL *cmd_tbl = ps->cmd_tbl;
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mem_memset(cmd_tbl, 0, sizeof(HBA_CMD_TBL) + sizeof(HBA_PRDT_ENTRY));
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uint64_t buf_phys = v2p((uint64_t)buffer);
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cmd_tbl->prdt[0].dba = (uint32_t)(buf_phys & 0xFFFFFFFF);
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cmd_tbl->prdt[0].dbau = (uint32_t)(buf_phys >> 32);
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cmd_tbl->prdt[0].dbc = (count * 512) - 1;
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cmd_tbl->prdt[0].i = 1;
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FIS_REG_H2D *fis = (FIS_REG_H2D*)&cmd_tbl->cfis;
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1;
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fis->command = ATA_CMD_WRITE_DMA_EX;
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fis->lba0 = (uint8_t)(lba);
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fis->lba1 = (uint8_t)(lba >> 8);
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fis->lba2 = (uint8_t)(lba >> 16);
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fis->device = 1 << 6;
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fis->lba3 = (uint8_t)(lba >> 24);
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fis->lba4 = (uint8_t)(lba >> 32);
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fis->lba5 = (uint8_t)(lba >> 40);
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fis->countl = (uint8_t)(count);
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fis->counth = (uint8_t)(count >> 8);
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port->ci = (1 << slot);
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int timeout = 1000000;
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while (timeout-- > 0) {
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if (!(port->ci & (1 << slot))) break;
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if (port->is & (1 << 30)) {
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serial_write("[AHCI] Write error on port ");
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serial_write_num(port_num);
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serial_write("\n");
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return -1;
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}
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}
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if (timeout <= 0) {
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serial_write("[AHCI] Write timeout on port ");
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serial_write_num(port_num);
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serial_write("\n");
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return -1;
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}
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return 0;
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}
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// ============================================================================
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// AHCI Disk Integration — wrap AHCI into Disk read/write_sector
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// ============================================================================
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typedef struct {
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int ahci_port;
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} AHCIDriverData;
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static int ahci_disk_read_sector(Disk *disk, uint32_t sector, uint8_t *buffer) {
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AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
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// For partitions, add offset and use parent's port
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if (disk->is_partition && disk->parent) {
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AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
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return ahci_read_sectors(pdata->ahci_port,
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(uint64_t)sector + disk->partition_lba_offset, 1, buffer);
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}
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return ahci_read_sectors(data->ahci_port, (uint64_t)sector, 1, buffer);
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}
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static int ahci_disk_write_sector(Disk *disk, uint32_t sector, const uint8_t *buffer) {
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AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
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if (disk->is_partition && disk->parent) {
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AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
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return ahci_write_sectors(pdata->ahci_port,
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(uint64_t)sector + disk->partition_lba_offset, 1, buffer);
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}
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return ahci_write_sectors(data->ahci_port, (uint64_t)sector, 1, buffer);
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}
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// ============================================================================
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// Initialization
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// ============================================================================
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int ahci_get_port_count(void) {
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return active_port_count;
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}
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bool ahci_port_is_active(int port_num) {
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if (port_num < 0 || port_num >= MAX_AHCI_PORTS) return false;
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return ports[port_num].active;
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}
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void ahci_init(void) {
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serial_write("[AHCI] Scanning PCI for AHCI controller...\n");
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// Find AHCI controller (Class 0x01, Subclass 0x06)
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pci_device_t pci_dev;
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if (!pci_find_device_by_class(PCI_CLASS_MASS_STORAGE, PCI_SUBCLASS_SATA, &pci_dev)) {
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serial_write("[AHCI] No AHCI controller found\n");
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return;
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}
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serial_write("[AHCI] Found AHCI controller (");
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serial_write("vendor=0x");
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serial_write_hex(pci_dev.vendor_id);
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serial_write(", device=0x");
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serial_write_hex(pci_dev.device_id);
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serial_write(")\n");
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// Enable Bus Mastering and MMIO
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pci_enable_bus_mastering(&pci_dev);
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pci_enable_mmio(&pci_dev);
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// Read ABAR (BAR5)
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uint32_t abar_raw = pci_get_bar(&pci_dev, 5);
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uint64_t abar_phys = abar_raw & 0xFFFFF000; // Mask out lower bits
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if (abar_phys == 0) {
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serial_write("[AHCI] Invalid ABAR address\n");
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return;
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}
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serial_write("[AHCI] ABAR physical address: 0x");
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serial_write_hex((uint32_t)abar_phys);
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serial_write("\n");
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// Map ABAR region into kernel virtual address space
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// Identity-map several pages to cover the HBA memory (at least 0x1100 bytes)
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uint64_t abar_virt = abar_phys; // Use identity mapping
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for (uint64_t offset = 0; offset < 0x2000; offset += 4096) {
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paging_map_page(paging_get_pml4_phys(), abar_virt + offset,
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abar_phys + offset,
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PT_PRESENT | PT_RW | PT_CACHE_DISABLE);
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}
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abar = (HBA_MEM*)abar_virt;
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// Enable AHCI mode
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abar->ghc |= (1 << 31); // AE (AHCI Enable)
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serial_write("[AHCI] Version: ");
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serial_write_num(abar->vs >> 16);
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serial_write(".");
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serial_write_num(abar->vs & 0xFFFF);
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serial_write("\n");
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// Probe ports
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uint32_t pi = abar->pi;
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active_port_count = 0;
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for (int i = 0; i < 32; i++) {
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ports[i].active = false;
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if (!(pi & (1 << i))) continue;
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HBA_PORT *port = &abar->ports[i];
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int type = ahci_check_port_type(port);
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if (type == 0) { // SATA drive
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serial_write("[AHCI] Port ");
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serial_write_num(i);
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serial_write(": SATA drive detected\n");
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ports[i].port_num = i;
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ports[i].port = port;
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ahci_port_rebase(&ports[i]);
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ports[i].active = true;
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active_port_count++;
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// Register as a block device
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Disk *disk = (Disk*)kmalloc(sizeof(Disk));
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if (disk) {
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AHCIDriverData *drv = (AHCIDriverData*)kmalloc(sizeof(AHCIDriverData));
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drv->ahci_port = i;
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disk->devname[0] = 0; // Auto-assign
|
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disk->type = DISK_TYPE_SATA;
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ahci_strcpy(disk->label, "SATA Drive");
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disk->read_sector = ahci_disk_read_sector;
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disk->write_sector = ahci_disk_write_sector;
|
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disk->driver_data = drv;
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disk->partition_lba_offset = 0;
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disk->total_sectors = 0;
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disk->parent = NULL;
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disk->is_partition = false;
|
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disk->is_fat32 = false;
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||||
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disk_register(disk);
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||||
|
||||
// Let disk_manager parse partitions — we call a scan function
|
||||
extern void disk_manager_scan_partitions(Disk *disk);
|
||||
// Inline MBR parse for this disk
|
||||
extern void serial_write(const char *str);
|
||||
serial_write("[AHCI] Probing partitions on /dev/");
|
||||
serial_write(disk->devname);
|
||||
serial_write("...\n");
|
||||
|
||||
// Read MBR sector 0
|
||||
uint8_t *mbr_buf = (uint8_t*)kmalloc(512);
|
||||
if (mbr_buf) {
|
||||
if (ahci_disk_read_sector(disk, 0, mbr_buf) == 0) {
|
||||
if (mbr_buf[510] == 0x55 && mbr_buf[511] == 0xAA) {
|
||||
// Parse MBR partition table
|
||||
typedef struct {
|
||||
uint8_t status;
|
||||
uint8_t chs_first[3];
|
||||
uint8_t type;
|
||||
uint8_t chs_last[3];
|
||||
uint32_t lba_start;
|
||||
uint32_t sector_count;
|
||||
} __attribute__((packed)) MBR_Part;
|
||||
|
||||
MBR_Part *parts = (MBR_Part*)&mbr_buf[446];
|
||||
int pn = 1;
|
||||
for (int p = 0; p < 4; p++) {
|
||||
if (parts[p].type == 0x00 || parts[p].sector_count == 0)
|
||||
continue;
|
||||
|
||||
bool fat32 = false;
|
||||
if (parts[p].type == 0x0B || parts[p].type == 0x0C) {
|
||||
// Verify BPB
|
||||
uint8_t *pbuf = (uint8_t*)kmalloc(512);
|
||||
if (pbuf) {
|
||||
if (ahci_disk_read_sector(disk, parts[p].lba_start, pbuf) == 0) {
|
||||
if (pbuf[510] == 0x55 && pbuf[511] == 0xAA) {
|
||||
uint16_t bps = *(uint16_t*)&pbuf[11];
|
||||
uint16_t spf16 = *(uint16_t*)&pbuf[22];
|
||||
uint32_t spf32 = *(uint32_t*)&pbuf[36];
|
||||
if (bps == 512 && spf16 == 0 && spf32 > 0)
|
||||
fat32 = true;
|
||||
}
|
||||
}
|
||||
kfree(pbuf);
|
||||
}
|
||||
}
|
||||
|
||||
disk_register_partition(disk, parts[p].lba_start,
|
||||
parts[p].sector_count, fat32, pn);
|
||||
pn++;
|
||||
}
|
||||
|
||||
// Fallback: raw FAT32
|
||||
if (pn == 1) {
|
||||
uint16_t bps = *(uint16_t*)&mbr_buf[11];
|
||||
uint16_t spf16 = *(uint16_t*)&mbr_buf[22];
|
||||
uint32_t spf32 = *(uint32_t*)&mbr_buf[36];
|
||||
if (bps == 512 && spf16 == 0 && spf32 > 0) {
|
||||
disk->is_fat32 = true;
|
||||
disk->partition_lba_offset = 0;
|
||||
serial_write("[AHCI] Raw FAT32 volume detected\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
kfree(mbr_buf);
|
||||
}
|
||||
}
|
||||
} else if (type == 1) {
|
||||
serial_write("[AHCI] Port ");
|
||||
serial_write_num(i);
|
||||
serial_write(": SATAPI drive (ignored)\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (active_port_count > 0) {
|
||||
ahci_initialized = true;
|
||||
serial_write("[AHCI] Initialization complete: ");
|
||||
serial_write_num(active_port_count);
|
||||
serial_write(" SATA port(s) active\n");
|
||||
} else {
|
||||
serial_write("[AHCI] No active SATA ports found\n");
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user